There is a popular call for CMOS (complementary metal oxide semiconductor) ICs (integrated circuits) design courses recently due to the global competition in IC chips. In PCB (printed circuit board) design, the layout, the circuits, interconnect routing etc. can be clearly visualized. However, this is not the case for ICs chips design, where all the circuits and interconnect are highly integrated down to the micro-meter or nano-meter ranges. The physical design cannot be visualized at all. This poses a very high challenging task in coaching the students in the ICs physical implementation. In this work, action research was carried out by introducing a physical 3D model of CMOS ICs as part of the ICs design lesson. Feedback was collected after the first lesson and improve the physical 3D model to better meet the expectation. A quick survey found that 100% of students prefer to have 3D model of CMOS layout to better understand the design. It is also interesting to find that nearly 75% prefer physical 3D model, and the rest found virtual 3D model could help as well. A cyber-physical model could be explored to meet all expectation, in the future work.
Tee Hui Teo, Singapore University of Technology & Design (SUTD), Singapore
Xiaoyu Lin, Singapore University of Technology & Design (SUTD), Singapore